The EM4100

Description

The EM4100 (previously named H4100)is a CMOS integrated circuit for use in electronic Read Only RF Transponders.
EM4100는 비교기 집적회로를 읽기 전용의 RF 응답기에 사용하기 위한 것이다.

The circuit is powered by an external coil placed in an electromagnetic field, and gets its master clock from the same field via one of the coil terminals.
이 회로의 전자기장은 외부의 코일로 이동되어 지고 이러한 자기장은 코일 단자중 하나를 통해서 마스터 클락으로 전해지게 된다.

By turning on and off the modulation current, the chip will send back the 64 bits of information contained in a factory pre-programmed memory array.
이것을 켜고 끄는 변화를 가해 줌으로 써, 이 칩은 미리 프로그램된 메모리 어레이에 포함된 64 비트의 정보를 다시 보내준다.

The programming of the chip is performed by laser fusing of polysilicon links in order to store a unique code on each chip.
칩의 프로그래밍은 주문 각각의 칩의 고유 코드를 저장하기 위해 폴리 실리콘 링크의 레이저 융합에 의해 수행된다.

The EM4100 has several metal options which are used to define the code type and data rate.
EM4100는 코드 유형과 데이터 속도를 정의하는 데 사용되는 몇 가지 옵션이 있다.

Data rates of 64, 32 and 16 periods of carrier frequency per data bit are available.
캐리어 주파수의 64, 32 및 16 비트의 Data rate들은 전송되는 신호 당 데이터 비트가 가능하다.

Data can be coded as Manchester, Biphase or PSK.
데이터는 맨체스터, Biphase 또는 PSK로 코딩 할 수 있다.

Due to low power consumption of the logic core, no supply buffer capacitor is required.
로직 코어의 낮은 전력 소비로 인해,  공급 버퍼는 콘덴서가 필요합니다.

Only an external coil is needed to obtain the chip function.
오직 외부 코일은 칩 기능을 얻기 위해 필요하다.

A parallel resonance capacitor of 74 pF is also integrated.
병렬 공명은 74 pF의 캐패시터도 통합되어 있다.

Features
특징

□ 64 bit memory array laser programmable
64 비트 메모리 어레이로 레이저 프로그램을 짤수 있다.

□ Several options of data rate and coding available
몇몇의 속도 데이터 및 코딩을 사용할 수 있는 옵션

□ On chip resonance capacitor
칩에 공명 캐패시터 있음.

□ On chip supply buffer capacitor
칩에 버퍼 캐패시터 공급됨.

□ On chip voltage limiter
칩에 전압 제한이 가능.

□ Full wave rectifier on chip
칩에 전파정류기 있음.

□ Large modulation depth due to a low impedance modulation device
대형 변조 깊이 장치 변조로 인해 낮은 임피던스

□ Operating frequency 100 - 150 kHz
작동 주파수 100 - 150 kHz

□ Very small chip size convenient for implantation
이식성이 좋은 작은 크기의 칩

□ Very low power consumption
저전력 소모

Applications
응용

□ Logistics automation
물류 자동화

□ Anticounterfeiting
위변조 불가

□ Access control
엑세스 제어

□ Industrial transponder
공업용의 자동응답기

Absolute Maximum Ratings
절대적인 최대 평가

Parameter	Symbol	Conditions
Maximum DC Current forced on COIL1 & COIL2 Power Supply Storage Temp. Die form Storage Temp. PCB form Electrostatic discharge maximum to MIL-STD-883C method 3015	ICOIL VDD Tstore Tstore VESD	±30mA -0.3 to 7.5V -55 to +200°C -55 to +125°C 1000V

Stresses above these listed maximum ratings may cause permanent damage to the device.
이것들 보다 초과하는 비율을 사용하게 되면 장치에 영구적인 손상을 가져오는 원인이 된다.

Exposure beyond specified operating conditions max affect device reliability or cause malfunction.
지정된 작동 조건의 최대치를 넘어가면 노출되는 장치의 신뢰성의 문제나 고장의 원인이 된다.

Operating Conditions
작동 조건

Parameter	Symbol	Min.	Typ.	Max.	Units
Operating Temp. Maximum Coil Current AC Voltage on Coil Supply Frequency	Top ICOIL Vcoil fcoil	-40 3 100	14*	+85 10 150	°C mA Vpp kHz

*) The AC Voltage on Coil is limited by the on chip voltage limitation circuitry. This is according to the parameter
코일에 교류 전압이 칩 전압 제한 회로에 의해 제한된다.

Handling Procedures
처리 절차

This device has built-in protection against high static voltages or electric fields; however due to the unique properties of this device, anti-static precautions should be taken as for any other CMOS component.
이 장치는 내장된 높은 정적 전압 또는 자기장에 대한 보호가 가능하지만 본 장치의 고유한 속성으로 인해, 정전기 예방 조치는 다른 비교기 구성 요소로 이동해야 가능해진다.

Electrical Characteristics
전기적 특성

VDD = 1.5V, VSS = 0V, fC1 = 134kHz square wave, Ta = 25°C

VC1 = 1.0V with positive peak at VDD and negative peak at VDD -1V unless otherwise specified

Parameter	Symbol	Test Conditions	Min.	Typ.	Max.	Units
Supply Voltage Rectified Supply Voltage Coil1 - Coil2 Capacitance Power Supply Capacitor	VDD VDDREC Cres Csup	VCOIL1 - VCOIL2 = 2.8 VDC Modulator switch = “ON” Vcoil=100mVRMS f=10kHz	1.5 1.5	74 2) 120	1)	V V pF pF
Biphase & Manchester Versions Supply Current C2 pad Modulator ON voltage drop C1 pad Modulator ON voltage drop	IDD VONC2 VONC1	VDD=1.5V IVDDC2=100μA with ref. to VDD VDD=5.0V IVDDC2=1mA with ref. to VDD VDD=5.0V IVDDC1=1mA with ref. to VDD	0.9 2.1 2.1	0.63 1.1 2.3 2.3	1.5 1.3 2.8 2.8	μA V V V
PSK Version Supply Current PSK C2 pad Modulator ON voltage drop	IDDPSK VONC2PSK	VDD=1.5V IVDDC2=100μA with ref. to VDD	0.3	0.92 0.6	2 0.9	μA V

Note 1) The maximum voltage is defined by forcing 10mA on COIL1 - COIL2
참고 1) 최대 전압은 코일1과 코일2의 10mA에 의해 강제로 정의 된다.

Note 2) The tolerance of the resonant capacitor is ± 15% over the whole production.
참고 2) 공진 콘덴서의 허용치는 ± 15 %

Optional reduced tolerance on request
옵션 요청에 대한 내성을 감소

On a wafer basis, the tolerance is ± 2%
웨이퍼 기준, 허용 오차는 ± 2 %이다

Timing Characteristics
타이밍 특성

VDD = 1.5V, VSS = 0V, fcoil = 134kHz square wave, Ta = 25°C

VC1 = 1.0V with positive peak at VDD and negative peak at VDD -1V unless otherwise specified

Timings are derived from the field frequency and are specified as a number of RF periods.
타이밍은 필드 주파수에서 파생된 RF 기간의 숫자로 지정된다.

Parameter	Symbol	Test Conditions	Value	Units
Read Bit Period	Trdb	depending on option	64, 32, 16	RF periods

Functional Description
기능 설명

General
일반 원칙

The EM4100 is supplied by means of an electromagnetic field induced on the attached coil.
EM4100은 첨부된 코일의 유도 전자기장에 의해 제공된다.

The AC voltage is rectified in order to provide a DC internal supply voltage.

 
When the last bit is sent, the chip will continue with the first bit until the power goes off.

Full Wave Rectifier

The AC input induced in the external coil by an incident magnetic field is rectified by a Graetz bridge.
 
The bridge will limit the internal DC voltage to avoid malfunction in strong fields.

Clock Extractor

One of the coil terminals (COIL1) is used to generate the master clock for the logic function.

The output of the clock extractor drives a sequencer.

Sequencer

The sequencer provides all necessary signals to address the memory array and to encode the serial data out.

Three mask programmed encoding versions of logic are available.

These three encoding types are Manchester, biphase and PSK. The bit rate for the first and the second type can be 64 or 32 periods of the field frequency.
 
For the PSK version, the bit rate is 16.

The sequencer receives its clock from the COIL1 clock extractor and generates every internal signal controlling the memory and the data encoder logic.

Data Modulator

The data modulator is controlled by the signal Modulation Control in order to induce a high current in the coil.

In the PSK version, only COIL2 transistor drives this high current.

In the other versions, both coil1 and coil2 transistors drive it to Vdd.

This will affect the magnetic field according to the data stored in the memory array.

Resonance Capacitor

This capacitor can be trimmed in factory by 0.5pf steps to achieve the absolute value of 74pf typically.
 
This option, which is on request, allows a smaller capacitor tolerance on the whole of the production.

Memory Array for Manchester & Bi-Phase encoding ICs

The EM4100 contains 64 bits divided in five groups of information.

9 bits are used for the header, 10 row parity bits (P0-P9), 4 column parity bits (PC0-PC3), 40 data bits (D00-D93), and 1 stop bit set to logic 0.

The header is composed of the 9 first bits which are all mask programmed to "1".

Due to the data and parity organisation, this sequence cannot be reproduced in the data string.

The header is followed by 10 groups of 4 data bits allowing 100 billion combinations and 1 even row parity bit.

Then, the last group consists of 4 event column parity bits without row parity bit. S0 is a stop bit which is written to "0"

Bits D00 to D03 and bits D10 to D13 are customer specific identification.

These 64 bits are outputted serially in order to control the modulator.

When the 64 bits data string is outputted, the output sequence is repeated continuously until power goes off.

Memory Array for PSK encoding ICs

The PSK coded IC's are programmed with odd parity for P0 and P1 and always with a logic zero.

The parity bits from P2 to P9 are even.

The column parity PC0 to PC3 are calculated including the version bits and are even parity bits.

Code Description

Manchester

There is always a transition from ON to OFF or from OFF to ON in the middle of bit period. At the transition from logic bit “1” to logic bit “0” or logic bit “0” to logic bit “1” the phase change.

Value high of data stream presented below modulator switch OFF, low represents switch ON

Biphase Code

At the beginning of each bit, a transition will occur.
 
A logic bit “1” will keep its state for the whole bit duration and a logic bit “0” will show a transition in the middle of the bit duration

PSK Code

Modulation switch goes ON and OFF alternately every period of carrier frequency.
 
When a phase shift occurs, a logical "0" is read from the memory.

If no shift phase occurs after a data rate cycle, a logical "1" is read